In a "flash"-type analog-to-digital converter the analog-to-digital conversion or comparison is ordinarily done in "parallel", i.e., in one step during one clock cycle. Flash-type analog to digital converters are known in the art, examples being the following:
637 Monolithic Expandable 6 Bit 20 MHZ CMOS/SOS A/D Converter", by Andrew G. F. Dingwall, IEEE Journal of Solid State Circuits, Vol, SC-14, no. 6, Dec. 1979, pp 926 to 932, herein after referred to as the Dingwall IEEE article.
Data Sheet for GE/RCA Models CA3318/CA3318A CMOS Video Speed 8 Bit Flash Analog-to-Digital Converter, published by and available from the manufacturer, herein after referred to as the CA3318 literature.
U.S. Pat. No. 4,612,531 Dingwall and Zazzu, "Intermeshed Resistor Network for Analog to Digital Conversion", issued on Sept. 16, 1986, herein after referred to as Dingwall and Zazzu.
Data sheet for Analog Devices Model CAV 1220 12 Bit Video Analog-to-Digital Converter contained in Analog Devices Databook, Copyright 1986, published by and available from the manufacturer, and herein after referred to as the CAV 1220 literature.
The "flash" type operation or parallel operation is in contrast to serial operation in which the comparisons or conversions are performed serially. The serial operation is necessarily much slower than the parallel operation and thus is not suitable for the high speed applications here contemplated.
The technology employed by the ADC of the Dingwall paper is silicon on sapphire (SOS) technology using complementary metal-oxide-silicon (CMOS) transistors. This is also the case for converters described in the CA3318 literature and in the Dingwall and Zazzu patent. In contrast, the technology employed in ADC of the CAV 1220 publication is essentially silicon using bipolar transistors in emitter-coupled-logic (ECL) configurations.
The Dingwall IEEE paper points that there are practical limits to the number of output bits that can be generated by a conventional flash-type x bit ADC, where x is the number of output bits. The number of comparators and the number of resistors in the resistive string (ladder) of the conventional ADC increases proportionally with the number of output bits. Assuming an available fixed reference potential is used across the resistor string, as the number of resistors increases, the voltage drop across each resistor decreases. This results in the comparators, which have a first input connected to the common node between adjacent resistors, needing to have increased sensitivity. In addition, the comparators draw some current out of the resistor string and introduce capacitive loading on the comparators. The presently accepted limiting value of the number of output bits of a flash type ADC is about eight. An 8 bit ADC typically requires a 256 resistor ladder and 255 comparators. The number of output bits determines the accuracy of the ADC. An 8 bit ADC is said to have 8 bit accuracy (one part in (256) A 12 bit ADC has 12 bit accuracy (one part in 4096).
Some applications require greater than eight bit accuracy. For example, for television video or radar application, twelve bit accuracy (one part in 4096) is typically needed; this is provided by the ADC described in the CAV 1220 literature and uses bipolar technology.
Another prior art solution used to obtain a twelve bit relatively fast and accurate ADC is to divide the ADC into two ADC's, the first being a five bit ADC and the second being an eight bit ADC with a needed subtraction function being accomplished by a 12 bit accuracy operational amplifier which has fast settling time. One of the bits of the 8 bit ADC is used for error correction such that the overall ADC has the five most significant bits generated by the first ADC and has the 7 least significant bits generated by the second ADC. One example of such an ADC is given in FIG. 1.
Referring now to FIG. 1, there is illustrated a prior art 12 bit Analog-to-Digital-Converter (ADC) 10. ADC 10 includes track circuitry 12 which has 12 bit accuracy, a capacitor C1, a clocked near unity gain buffer circuit 14, a 5 Bit Analog-to-Digital Convertor (ADC) 16 with an accuracy of plus or minus 1/2 least significant bit, an analog delay element 20, a digital delay element 23, error correction circuitry 24, a 5 bit Digital-to-Analog-Convertor (DAC) 26 with a 12 bit accuracy, a two input operational amplifier 28 characterized by 12 bit accuracy and fast settling time, an 8 bit Analog-to-Digital-Convertor (ADC) 29. Track circuitry 12 and capacitor C1 provide a track and hold function. ADC 16 includes a resistor string including resistors R1, R2, . . . and R32, comparators 1, 2, . . . and 31, first bar code to binary circuitry 18 and first latch circuitry 22. ADC 29 includes a resistor string and 255 comparators 30, a second bar code to binary circuitry 32, an inverter circuit 34, and second latch circuitry 36. ADC 10 receives an analog signal at an input terminal Vin and generates a 12 bit digital output signal having the five most significant bits MSB1, MSB2, MSB3, MSB4, MSB5 being generated at an output of error correction circuitry 24 and having the seven least significant bits LSB1, LSB2, LSB3, LSB4, LSB5, LSB6 and LSB7 generated at the output of latch circuitry 36.
An analog signal applied to input terminal Vin is allowed to selectively charge C1 to a potential level corresponding to the average voltage level of the input analog signal during a preselected time period. An output of unity gain buffer circuit 14 is coupled to an input of analog delay element 20 and to first inputs of each of comparators 1, 2, . . . and 31. After C1 is so charged, buffer circuit 14 is then clocked on by a signal applied to a clock terminal 14a thereof. This allows the potential level of C1 to be coupled to an input of each of the 31 comparators of ADC 16 and to an input of the analog delay element 20. ADC 16 generates on output terminals of the comparators 1, 2, . . . 31 an output bar code signal which is coupled to input terminals of bar code to binary circuitry 18. Bar code to binary circuitry 18 generates at five output terminals thereof, five output digital signals which are coupled to five input terminals of latch circuitry 22. Five output terminals of latch circuitry 22 are connected to five separate input terminals of DAC 26 and to five separate input terminals of error correction circuitry 24. Information from latch circuitry 22 coupled to DAC 26 and to error correction circuitry 24 when is appropriately conditioned by a clock signal applied to a clock terminal 22a thereof.
An output of DAC 26 is connected to a positive input terminal of operational amplifier 28. An output of analog delay element 20 is coupled to a negative input terminal of operational amplifier 28. An output of operational amplifier 28 is connected to a first input terminal of each of the 255 comparators of ADC 29.
Five Bit DAC 26, which has 12 bit accuracy, generates an analog signal from the five bit digital signals received from bar-code-to-binary circuitry 18 via latch circuitry 22. Operational amplifier 28 effectively subtracts with 12 bit accuracy the "range estimate" output of DAC 26 from the output of analog delay element 20 to generate at an output terminal thereof a resultant analog "residue" signal that serves as an input signal to ADC 29. The 255 comparators of ADC 29 output signals which are coupled to 255 inputs of bar code to binary circuitry 32. Bar code to binary circuitry 32 has eight output terminals. The first six outputs of bar code to binary circuitry 32 are connected to six input terminals of latch circuitry 36. The seventh output terminal of bar code to binary circuitry 32 is coupled to an input terminal of inverter circuit 34 which has an output connected to a seventh input of latch circuitry 36. The seventh and eighth outputs of bar code to binary circuitry 32 are connected to two inputs of overrange/underrange error correction circuitry 24.
ADC 10 generates a 12 bit output digital signal which is a digital representation of an analog signal applied to the input terminal Vin of ADC 10. At seven outputs of latch circuitry 36 there are generated the seven least significant bits LSB1, LSB2, LSB3, LSB4, LSB5, LSB6 and LSB7 of the desired 12 bit digital output signal of ADC 10. At five outputs of error correction circuitry 24 there are generated the five most significant bits, MSB1, MSB2, MSB3, MSB4, MSB5 of the desired 12 bit digital output signal ADC 10.
Track circuit 12 and DAC 26 must be of 12 bit accuracy and therefore they are relatively complex and expensive to construct. Operational amplifier 28 must also have 12 bit accuracy and must also have a fast settling time in order to allow high frequency operation of ADC 10. Operational amplifier 28 is typically relatively complex and relatively expensive to construct. Accordingly, it is desirable to be able to have a circuitry which performs the basic functions of track circuitry 12, capacitor C1, clocked unity gain buffer circuit 14, DAC 26, operational amplifier 28, and analog delay element 20 and which is significantly less complex and expensive. Another problem is that in order to get the accuracy needed by operational amplifier 28, it is typically fabricated using bipolar circuitry whereas most of the balance of ADC 10 can be fabricated from metal-oxide-semiconductor (e.g., silicon) (MOS) devices or complementary MOS (CMOS) devices. Since it is difficult to fabricate high performance bipolar and MOS devices on the same integrated circuit, operational amplifier 28 is typically formed on a separate integrated circuit than most other components of ADC 10. It is desirable to be able to construct most, if not all, of the components of a 12 bit fast ADC on one integrated circuit which uses MOS compatible technology.